Register Transfer Logic (RTL) describes data flow between registers and how logical and mathematical operations are applied. Engineers use RTL design to describe functional blocks, defining the behavior of a discrete component used to perform a specific function. Each functional block has a description of the registers within the block, called the sequential circuit, and a combinational circuit containing the logic for the functional block. Hardware Description Language (HDL) describes how functional blocks connect to define data flow.
RTL design’s power lies in dividing complex systems into simpler blocks represented by HDL code. Here are some fundamental concepts:
Registers
In RTL design, a hardware element storing a specific amount of data is called a register, often implemented as D flip-flops. A register’s value can be read as input to a logic operation or set as the output. Characterizing how data flows between registers and how operations modify data is fundamental to RTL design.
Hardware Description Language (HDL)
Crucial to RTL design is the code describing circuit behavior. HDL is a specialized language resembling a programming language, with variables, function calls, logic statements (if-then-else, CASE), and Boolean and mathematical statements. However, HDL describes the behavior and structure of electronic circuits, typically integrated circuits. A key difference is the inclusion of time, allowing operations to be triggered by clock pulses.
This is done using a variable representing the digital clock’s value, as in this simple VHDL inverter example, where the output (Q) is set to the input (D) when the clock (clk) transitions from low to high (rising edge):
D
process(clk) begin if rising_edge(clk) then Q end if; end process;
VHDL (Very High-Speed Integrated Circuit Hardware Description Language) is verbose and strongly typed, with a non-C-like syntax. It’s preferred for describing complex system designs.
Verilog, or its extension SystemVerilog, is another popular HDL. It’s more concise, weakly typed, flexible, and has a C-like syntax. Its ease of learning and description makes it preferable for beginners or less complex circuits. Both Verilog and VHDL are IEEE industry standards.
Here’s a simple AND gate example in both languages. An AND gate has two inputs and one output; if both inputs are 1, the output is 1. Otherwise, the output is 0.
Logic Operations
RTL design uses two types of operations. Logic operations perform bitwise evaluations and modify data in registers. Logic operations like AND, OR, NOT, XOR, and shift are created by defining logic behavior in HDL. The example above shows AND representation in VHDL and Verilog. Logic operations represent logic gates in hardware.
Arithmetic Operations
The second type is arithmetic operations, which perform addition, subtraction, multiplication, and division on data in registers. They are represented in HDL using standard mathematical operators. For example, adding two numbers in VHDL would use:
rst
— where inp1 and inp2 are input registers and rst is assigned to the output register. Arithmetic operations in RTL represent dedicated hardware elements like adders, subtractors, multipliers, and dividers.
Synchronous and Asynchronous Actions
RTL design can represent data flow synchronously or asynchronously. For synchronous operation, a subroutine is executed or triggered by the system clock input to the function. For asynchronous operation, the subroutine is executed when the value of one or more input ports changes in a specific way. This is accomplished by checking the input values of either the clock input or non-clock inputs to see if they change using an if statement.
